Circuit design method, apparatus, and program

ABSTRACT

A circuit design method able to design a processing circuit to be small in scale when designing a processing circuit for performing a plurality of different processings on predetermined data, comprising a first step of identifying second processings performing the same processing on the same data among pluralities of second processings forming each of a plurality of first processings when designing a processing circuit for applying a plurality of different first processings on predetermined data and a second step of designing a processing circuit having a processing circuit shared by the plurality of first processings and for performing the second processings identified at the first step.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method, apparatus, and program for designing a processing circuit for performing processing such as a linear transform as used in for example error correction coding and decoding.

[0003] 2. Description of the Related Art

[0004] For example, in error correction coding and decoding of the Hamming code etc., various types linear transform processings are performed in a linear space defined on a finite field.

[0005] In such linear transform processing, for example, a predetermined base on the linear space is used to express a dimension on the linear space by a vector and linear transform processing is applied to this vector to obtain a new vector.

[0006] In the above-mentioned error correction coding and decoding, for example, sometimes a plurality of bits of predetermined data are subjected to a plurality of processings for different linear transforms.

[0007] Conventionally, for example, a processing circuit is designed to perform this plurality of processings independently.

[0008] Summarizing the problem to be solved by the invention, however, as explained above, if designing a processing circuit to perform the above plurality of processings independently, the processing circuit becomes large in scale.

SUMMARY OF THE INVENTION

[0009] An object of the present invention is to provide a circuit design method, apparatus, and program able to design a processing circuit to be small in scale when designing a processing circuit to perform a plurality of different processings on predetermined data.

[0010] According to a first aspect of the invention, there is provided a circuit design method executed by computer for designing a processing circuit for applying a plurality of different first processings to predetermined data comprising a first step of identifying second processings performing the same processing on the same data in pluralities of second processings forming each of the plurality of first processings and a second step of designing a processing circuit comprising a first processing circuit shared by the plurality of first processings and performing the second processings identified in the first step and a second processing circuit for performing processings other than the second processings identified in the first step in the pluralities of second processings forming each of the plurality of first processings.

[0011] That is, in the circuit design method of the first aspect of the invention, first, in a first step, second processings performing the same processing on the same data are identified among pluralities of second processings forming each of a plurality of first processings.

[0012] Then, in a second step, the processing circuit comprising a first processing circuit shared by the plurality of first processings and performing the second processings identified in the first step and a second processing circuit for performing processings other than the second processings identified in the first step among the pluralities of second processings forming each of the plurality of first processings is designed.

[0013] According to a second aspect of the invention, there is provided a circuit design apparatus of a processing circuit for applying a plurality of different first processings to predetermined data comprising a first means for identifying second processings performing the same processing on the same data in pluralities of second processings forming each of the plurality of first processings and a second means for designing a processing circuit comprising a first processing circuit shared by the plurality of first processings and performing the second processings identified by the first means and a second processing circuit for performing processings other than the second processings identified by the first means in the pluralities of second processings forming each of the plurality of first processings.

[0014] In the circuit design apparatus of the second aspect of the invention, a first means identifies second processings performing the same processing on the same data among the pluralities of second processings forming each of the plurality of first processings.

[0015] A second means designs a processing circuit comprising a first processing circuit shared by the plurality of first processings and performing the second processings identified by the first means and a second processing circuit for performing processings other than the second processings identified by the first means among the pluralities of second processings forming each of the plurality of first processings.

[0016] According to a third aspect of the invention, there is provided a program executed in a circuit design apparatus of a processing circuit for applying a plurality of different first processings to predetermined data comprising a first routine of identifying second processings performing the same processing on the same data in pluralities of second processings forming each of the plurality of first processings and a second routine of designing a processing circuit comprising a first processing circuit shared by the plurality of first processings and performing the second processings identified in the first routine and a second processing circuit for performing processings other than the second processings identified in the first routine in the pluralities of second processings forming each of the plurality of first processings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above object and features of the present invention will be more apparent from the following description of the preferred embodiments given with reference to the accompanying drawings, wherein:

[0018]FIG. 1 is a view for explaining the related art of the present invention;

[0019]FIG. 2 is a view for explaining the related art of the present invention;

[0020]FIG. 3 is a diagram for explaining the related art of the present invention;

[0021]FIG. 4 is a view for explaining the related art of the present invention;

[0022]FIG. 5 is a view for explaining the related art of the present invention;

[0023]FIG. 6 is a view for explaining peripheral circuits of a processing circuit designed by a circuit design method of a first embodiment of the present invention;

[0024]FIG. 7 is a view for explaining a computer for executing the circuit design method of the first embodiment of the present invention;

[0025]FIG. 8 is a flow chart for explaining a case of designing a processing circuit by the procedure of the circuit design method of the first embodiment of the present invention;

[0026]FIG. 9 is a view for explaining a processing circuit designed by the circuit design method of the first embodiment of the present invention;

[0027]FIG. 10 is a view for explaining a data output timing of the processing circuit shown in FIG. 9;

[0028]FIG. 11 is a view for explaining a concrete example of the processing circuit shown in FIG. 9;

[0029]FIG. 12 is a view for explaining a processing circuit for performing γ^(r) to γ^(kr)-times multiprocessings (xγ^(r)) defined by the circuit design method of the first embodiment of the present invention;

[0030]FIG. 13 is a view for explaining the related art of a circuit design method of a second embodiment of the present invention; and

[0031]FIG. 14 is a view for explaining the circuit design method of the second embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Before giving an explanation of embodiments of the present invention, a more detailed explanation will be given of the related art for reference purposes.

[0033] [Related Art of Invention]

[0034]FIG. 1 is a view of the configuration of a processing circuit 101 according to a related art of the present invention.

[0035] The processing circuit 101 receives as input the data “a” and outputs the data b₁ to b_(k).

[0036] The processing circuit 101 has a plurality of systems of processing circuit modules for sequentially performing processings C_(i,l) to C_(i,li) defined by matrixes M_(i,l) to M_(i,li) in the systems, where “i” is a natural number of 2 or more satisfying 1≦i≦k, and l_(i) is a natural number. These processing circuit modules perform processings in parallel.

[0037] The processing modules are configured by directly connecting a plurality of processing circuits 2 il _(j) for performing processings C_(i,l) to C_(i,lj).

[0038] The processing circuit 101 receives as input the data “a” expressed by a vector by a base on the linear space, applies linear processing to the data “a” in the processing circuits 21 l ₁ to 2 kl _(k), and outputs b₁ to b_(k) from the processing circuits 21 l ₁ to 2 kl _(k).

[0039] The processing circuit 1 shown in FIG. 1 can achieve a reduction of size and increase of speed by designing it like the processing circuit 201 using the processing circuit modules il_(j) (j is integer of 2 or more) combining the processings C_(i,1) to C_(i,1i) in the processing circuit modules as shown in FIG. 2.

[0040] In this case, linear transform strings defined as shown in FIG. 2 and the following (1-1) are combined as shown in the following (1-2): $\begin{matrix} \begin{matrix} {\left\{ {C_{1,1},C_{1,2},{\ldots \quad C_{1,11}}} \right\},} \\ {\left\{ {C_{2,1},C_{2,2},{\ldots \quad C_{2,12}}} \right\},} \\ {\cdots \quad \cdots \quad \cdots \quad \cdots} \\ {\left\{ {C_{k,1},C_{k,2},{\ldots \quad C_{1,{1k}}}} \right\},} \\ {\left\{ {{Range}\quad {of}\quad C_{i,{j - 1}}} \right\} \Subset \left\{ {{Domain}\quad {of}\quad C_{i,j}} \right\}} \end{matrix} & \left( {1\text{-}1} \right) \\ \begin{matrix} {C_{1,11} \circ \ldots \quad \circ C_{1,2} \circ {C_{1,1}:\left. a\mapsto b_{1} \right.}} \\ {C_{2,12} \circ \ldots \quad \circ C_{2,2} \circ {C_{2,1}:\left. a\mapsto b_{2} \right.}} \\ \cdots \\ {C_{k,{1k}} \circ \ldots \quad \circ C_{k,2} \circ {C_{k,1}:\left. a\mapsto b_{k} \right.}} \end{matrix} & \left( {1\text{-}2} \right) \end{matrix}$

[0041] In this specification “X

Y” means “Y” is obtains by performing a corresponding operation with respect to “X”.

[0042] At this time, when making the processings C_(i,l) to C_(i,li) shown in the above (1-1) the matrix M_(i,l) to M_(i,li) for linear transforms, the above (1-1) and (1-2) are indicated as in the following (1-3) and (1-4): $\begin{matrix} \begin{matrix} {\left\{ {M_{1,1},M_{1,2},{\ldots \quad M_{1,11}}} \right\},} \\ {\left\{ {M_{2,1},M_{2,2},{\ldots \quad M_{2,12}}} \right\},} \\ {\cdots \quad \cdots \quad \cdots \quad \cdots} \\ \left\{ {M_{k,1},M_{k,2},{\ldots \quad M_{1,{1k}}}} \right\} \end{matrix} & \left( {1\text{-}3} \right) \\ \begin{matrix} {M_{1}:={M_{1,11}\ldots \quad M_{1,2}{M_{1,1}:\left. a\mapsto b_{1} \right.}}} \\ {M_{1}:={M_{2,12}\ldots \quad M_{2,2}{M_{2,1}:\left. a\mapsto b_{2} \right.}}} \\ \cdots \\ {M_{k}:={M_{k,{1k}}\ldots \quad M_{k,2}{M_{k,1}:\left. a\mapsto b_{k} \right.}}} \end{matrix} & \left( {1\text{-}4} \right) \end{matrix}$

[0043] By this, the processing circuit 201 can be designed as a circuit for the matrix shown in the following (1-5): $\begin{matrix} {M:={\begin{pmatrix} M_{1} \\ M_{2} \\ \cdots \\ M_{k} \end{pmatrix}:\left. a\mapsto\begin{pmatrix} b_{1} \\ b_{2} \\ \cdots \\ b_{k} \end{pmatrix} \right.}} & \left( {1\text{-}5} \right) \end{matrix}$

[0044] Next, an explanation will be given of the design method for a processing circuit for performing a plurality of processings comprising applying first linear transforms D different predetermined numbers of times to the input data FS0 and outputting data b₁ to b_(k) as the results of the related processings.

[0045]FIG. 3 is a view for explaining such a processing circuit 301 and the peripheral circuits thereof.

[0046] As shown in FIG. 3, a selector 312 selects one data between the input data “a” and the data MLS on the basis of a selection signal SEL and outputs the related selected data FS0 to a register 313 ₀ and a processing circuit 301.

[0047] The processing circuit 301 performs a plurality of processings for applying first linear transforms D different predetermined numbers of times to the data FS0 input from the selector 312 and outputs the data b₁ to b_(k) as the results of the processings to the registers 313 ₁ to 313 _(k).

[0048] The registers 313 ₁ to 313 _(k) hold the input data FS0 and b₁ to b_(k) and output them as data OUT₁ to OUT_(k) at predetermined timings.

[0049] The processing circuit 314 receives as input the data OUT_(k), applies the first linear processing D to this, and outputs the data MSL as the result thereof to the selector 312.

[0050] The processing circuit 301 is designed, for example as shown in FIG. 3, by serially connecting a plurality of processing circuits 321 ₁ to 321 _(k) for performing linear transforms D, inputting the data “a” to the first stage circuit 321 ₁, and outputting the data b₁ to b_(k) generated at individual processing circuits 321 ₁ to 321 _(k) to the registers 313 ₁ to 313 _(k).

[0051] Here, the processing circuit 301 shown in FIG. 3 is designed as shown in FIG. 4 where it performs α-times multiprocessings on the dimension of the finite field F(2⁴), i.e., α, α²+α+1=0.

[0052] In this case, as shown in FIG. 3, for the data “a” input at a certain timing, the data OUT₀, OUT₁, and OUT₂ become as follows:

[0053] OUT₀: a, a*α^(k+1), a*α^(k+2), . . . ,

[0054] OUT₁: a*α, a*α^(K+2), a*α^(2K+3), . . . ,

[0055] OUT₂: a*α², a*α^(K+3), a*α^(2K+4), . . . ,

[0056] Here, where FS0=A0+A1α, these become as follows:

[0057] FS0·α=A1+(A0+A1)α

[0058] FS0·α²=(A0+A1)+A0α

[0059] Accordingly, the processing circuits 321 ₁ and 321 ₂ shown in FIG. 4 are individually designed by the adder circuits 351 ₁ and 351 ₂ as shown in FIG. 5.

[0060] As mentioned above, however, there is a problem in that the circuit scale becomes large when designing the processing circuit 301.

[0061] Further, in the processing circuit 301, there is a problem in that the time from when the data “a” is input to the first stage circuit 321 ₁ to when the data b_(k) is output from the final stage circuit 321 _(k) becomes long, so a high performance processing circuit 301 cannot be designed.

[0062] Below, an explanation will be given of an embodiment of the present invention for solving the problems of the related art mentioned above.

[0063] [First Embodiment]

[0064]FIG. 6 is a view for explaining peripheral circuits of a processing circuit 11 designed by the circuit design method of the present embodiment.

[0065] As shown in FIG. 6, a selector 12 selects one data between the input data “a” and the data MLS on the basis of a selection signal SEL and outputs the selected data FS0 to a register 13 ₀ and the processing circuit 11.

[0066] The processing circuit 11 performs a plurality of processings for applying first linear transforms D different predetermined numbers of times to the data FS0 input from the selector 12 and outputs the data b₁ to b_(k) as the results of the processings to the registers 13 ₁ to 13 _(k).

[0067] The registers 13 ₁ to 13 _(k) hold the input data FS0 and b₁ to b_(k) and output them as data OUT₁ to OUT_(k) at predetermined timings.

[0068] The processing circuit 14 receives as input the data OUT_(k), applies the first linear processing D to this, and outputs the data MSL as the result thereof to the selector 12.

[0069] The circuit design method of the present embodiment designs the processing circuit 11 shown in FIG. 6.

[0070] In the present embodiment, when the predetermined linear space is an m-th enlargement of a finite field F_(q), where “q” is the prime number and the dimension thereof is expressed by the m-th dimension vector on F_(q), the predetermined linear space is indicated by the following (2-1) or F(q^(m))

Linear space Fg^(m)  (2-1)

[0071] Further, using the base shown in the following (2-2) as the predetermined base, the data “a” of the predetermined data is indicated as in the following (2-3) on a basis of the base shown in the following (2-2):

{γ₁, γ₂, . . . , γ_(m)}  (2-2)

a=a₁γ₁+a₂γ₂+ . . . a_(m)γ_(m)  (2-3)

[0072] Further, using the data “a” as the m-th dimension vector, the result becomes as in the following (2-4): $\begin{matrix} {a = \begin{pmatrix} a_{1} \\ a_{2} \\ \vdots \\ a_{m} \end{pmatrix}} & \left( {2\text{-}4} \right) \end{matrix}$

[0073] Further, the first linear transform D is defined as the linear transform D on the linear space shown in the above (2-1).

[0074] Further, the data “b” of the result of the above plurality of processings is shown as the k-th dimension vector by the following (2-5) and the data bi indicating the results of the processings forming the data “b” shown in the following (2-5) is shown as the di-th dimension vector by the following (2-6):

[0075] Here, “m” and di are integers of 2 or more, the predetermined number of times corresponding to at least one of the above plurality of processings is 2 or more, and “k” is an integer of 2 or more. $\begin{matrix} {b = \begin{pmatrix} b_{1} \\ b_{2} \\ \vdots \\ b_{k} \end{pmatrix}} & \left( {2\text{-}5} \right) \\ {b_{i} = \begin{pmatrix} b_{i,1} \\ b_{i,2} \\ \vdots \\ b_{i,{di}} \end{pmatrix}} & \left( {2\text{-}6} \right) \end{matrix}$

[0076] Here, when making the above plurality of processings OP₁ to OP_(K), they are indicated by the following (3-7): $\begin{matrix} \begin{matrix} {{{OP}_{1}:\left\{ D \right\}},} & {D:} & \left. a\mapsto b_{1} \right. \\ {{{OP}_{2}:\left\{ {D,D} \right\}},} & {D^{2}:={D \circ {D:}}} & \left. a\mapsto b_{2} \right. \\ {{{OP}_{3}:\left\{ {D,D,D} \right\}},} & {D^{3}:={D \circ D \circ {D:}}} & \left. a\mapsto b_{2} \right. \\ {\cdots \quad \cdots} & {\cdots \quad \cdots} & {\cdots \quad \cdots} \\ {{{OP}_{k}:\left\{ {D,D,D,\ldots \quad,D} \right\}},} & {D^{k}:={D \circ D \circ D \circ \quad \ldots \quad \circ {D:}}} & \left. a\mapsto b_{k} \right. \end{matrix} & \left( {2\text{-}7} \right) \end{matrix}$

[0077] Then, when making the matrix comprised by “di” rows and “m” columns expressing the first linear transform D Md, the above (2-7) is indicated by the following (2-8): $\begin{matrix} \begin{matrix} {\left\{ M_{d} \right\},} & {M_{d}:\left. a\mapsto b_{1} \right.} \\ {\left\{ {M_{d},M_{d}} \right\},} & {M_{d}^{2}:\left. a\mapsto b_{2} \right.} \\ {\left\{ {M_{d},M_{d},M_{d}} \right\},} & {M_{d}^{3}:\left. a\mapsto b_{3} \right.} \\ {\cdots \quad \cdots \quad \cdots} & \quad \\ {\left\{ {M_{d},M_{d},M_{d},\ldots \quad,M_{d}} \right\},} & {M_{d}^{k}:\left. a\mapsto b_{k} \right.} \end{matrix} & \left( {2\text{-}8} \right) \end{matrix}$

[0078] A matrix M of k·dixm obtained by vertically arranging the matrixes Md to Md^(k) comprised of “di” rows and “m” columns expressing the combination of the transform strings defined by the above OP₁ to OP_(K) is shown by the following (2-9): $\begin{matrix} {M:={{\begin{pmatrix} M_{d} \\ M_{d}^{2} \\ \cdots \\ M_{d}^{k} \end{pmatrix}:\left. a\mapsto\begin{pmatrix} b_{1} \\ b_{2} \\ \cdots \\ b_{k} \end{pmatrix} \right.} = \begin{pmatrix} {D \cdot a} \\ {D^{2} \cdot a} \\ \cdots \\ {D^{k} \cdot a} \end{pmatrix}}} & \left( {2\text{-}9} \right) \end{matrix}$

[0079] As shown in the above (2-9), the matrix M defines “k: number of processings for the first linear transform and the second transforms D² to D^(k) on the data “a”.

[0080]FIG. 7 is a view for explaining the computer 29 for executing the circuit design method of the present embodiment.

[0081] As shown in FIG. 7, the computer 29 has for example an operating unit 31, a display 32, a memory 33, and a CPU 34 all connected via a bus 30.

[0082] The operating unit 31 is an operating means such as a keyboard or a mouse and is used for instructing execution of the program, instructing selection of data, and inputting data at the CPU 34.

[0083] The display 32 displays the processing results of the CPU 34.

[0084] The memory 33 stores a program 41 to be executed by the CPU 34 and data 42 used for the execution of the program 41.

[0085] The CPU 34 executes the program 41 to perform the following processings and uses the data 42 in the process of execution of the program 41 for processing for designing the circuit of the processing circuit 11.

[0086] The program 41 corresponds to the program of the present invention and describes routines indicating the contents of the following steps.

[0087] Further, the circuit design apparatus of the present invention is configured by the CPU 34 executing the program 41. The CPU 34 executes step ST12 to design the first means of the present invention, and the CPU 34 executes step ST13 to design the second means of the present invention.

[0088] Below, an explanation will be given of an example of the operation of the circuit design method of the present embodiment in relation to the processing of the CPU 34.

[0089]FIG. 8 is a flow chart for explaining an example of the operation of the circuit design method of the present embodiment.

[0090] Step ST11

[0091] The CPU 34 receives as input the data for defining the formats of the input and the output of the processing performed by the processing circuit 11 as shown in the above (2-4), (2-5), and (2-6) and the contents of a plurality of processings for applying a number of first linear transforms D corresponding to the predetermined number of times of processing by the processing circuit 11 to the data “a” as shown in the above (2-7) in accordance with an operation by the user on the operating unit 31.

[0092] Step ST12

[0093] The CPU 34 performs the processing for generating the matrix M indicated in the above (2-9) for performing the second linear transform (first processing) obtained by combining a number of the first linear transforms D corresponding to the above predetermined number of times for each of the plurality of processings performed by the processing circuit 11 shown in the above (2-7) input at step ST11.

[0094] Step ST13

[0095] The CPU 34 identifies the second processings performing the same processing on the same data among the pluralities of second processings forming each of the plurality of second linear transforms (first processings) defined at the above step ST12.

[0096] Step ST14

[0097] The CPU 34 designs a processing circuit 11 shown in FIG. 9 comprised of a first processing circuit shared by the plurality of second linear transforms (first processings) and performing the second processings identified at step ST13 and a second processing circuit for performing the processings other than the above second processings identified at step ST13 among the above pluralities of second processings forming each of the above plurality of first processings.

[0098] At this time, the CPU 34 generates the design data of the processing circuit 11 so as to perform “k” number of processings for performing the first linear transforms D to D^(k) on the data FS0 in parallel on the basis of the matrix M generated at step ST12 shown in the above (2-9).

[0099] Concretely, the CPU 34 generates the design data indicating the design of the processing circuit 11 comprised of the processing circuits 21 ₁ to 21 _(k) for performing the first linear transforms D to D^(k) on the data FS0 arranged in parallel as shown in FIG. 9.

[0100] By this, the CPU 34 generates the design data of the processing circuit 11 designed so as to apply the linear transforms defined by the matrix M indicated by above (2-9) to the input data FS0 and to output the data b₁ to b_(k).

[0101] By designing the processing circuit 11 as shown in FIG. 9, the outputs from the registers 13 ₀ to 13 _(k) become as shown in FIG. 10 plotting the time in the lateral direction.

[0102] Namely, the data b₁ to b_(k) are output from the processing circuit 1 at approximately the same timing, so the data OUT₀ to OUT_(K) are also output at approximately the same timing.

[0103] At this time, the relationships among the processing of the matrix M performed by the processing circuit 11, the data FS0 input to the processing circuit 11, and the data OUT₀ to OUT_(K) are indicated by the following (2-10): $\begin{matrix} {{M \cdot {FSO}} = {\begin{pmatrix} {D \cdot {FSO}} \\ {D^{2} \cdot {FSO}} \\ {D^{3} \cdot {FSO}} \\ \vdots \\ {D^{K} \cdot {FSO}} \end{pmatrix} = \begin{pmatrix} {OUT}_{0} \\ {OUT}_{1} \\ {OUT}_{2} \\ \vdots \\ {OUT}_{k} \end{pmatrix}}} & \left( {2\text{-}10} \right) \end{matrix}$

[0104] Here, the matrix M is comprised by the dimension of the linear space defined by the above (2-1), so the data OUT₁ to OUT_(K) (data b_(l) to b_(k)) are defined as the product of the dimension of the linear space and elements of the data FS0 and the sum of the same. For this reason, the combinations become finite at most. For example, when the value “k” is large with respect to the value “m”, as shown in FIG. 8, by feeding back the data b_(k) output from the processing circuit 11 via the processing circuit 14 and the selector 12 to the processing circuit 11, a processing circuit 11 able to cope with a variety of processings can be constructed with a small scale design.

[0105] Below, when the processing circuits 21 ₁ and 21 _(K) of the processing circuit 11 shown in FIG. 9 perform α-times multiprocessing with respect to the dimensions of the finite field F(2⁴), i.e., α, α²+α+1=0, they are designed like the processing circuit 221 shown in FIG. 11.

[0106] In this case, as shown in FIG. 3, for the data “a” input at a certain timing, the data OUT₀, OUT₁, and OUT₂ become as follows:

[0107] OUT₀: a, a*α^(k+1), a*α^(2k+2), . . . ,

[0108] OUT₁: a*α, a*α^(k+2), a*α^(2k+3), . . . ,

[0109] OUT₂: a*α², a*α^(k+3), a*α^(2k+4), . . . ,

[0110] Namely, when FS0=A0+A1α, the data OUT₀, OUT₁, and OUT₂ in the next clock cycle become as follows:

[0111] OUT₀: FS0=A0+A1α

[0112] OUT₁: FS0·α=A₁+(A₀+A1)α

[0113] OUT₂: FS0·α·α=(A0+A1)+A0α

[0114] In this case, at step ST13 shown in FIG. 8 mentioned above, the CPU 34 identifies the second processings performing the same processing on the same data among the plurality of second processings forming the above α-times multiprocessings, that is, the processing “A0+A1”.

[0115] Then, at step ST14 shown in FIG. 8, the CPU 34 designs a processing circuit 11 a shown in FIG. 11 comprising a first processing circuit 115 shown in FIG. 11 (adder circuit in FIG. 11) shared by a plurality of α-times multiprocessings (that is, α-times multiprocessing and α²-times multiprocessing) and performing the processing “A0+A1” identified at step ST13 and a second processing circuit shown in FIG. 11 (none in the example shown in FIG. 11) for performing the processings other than the above second processings identified at step ST13 among the above pluralities of second processings forming each of the plurality of α-times multiprocessings.

[0116] Note that, in the above embodiment, when the above first linear transform is for performing the γ^(r)-times multiprocessings (xγ^(r)) with respect to the dimension γ of the linear space identified in the above (2-1), if the plurality of processings are OP₁ to OP_(K), they are indicated by the following (2-11): $\begin{matrix} {{{OP}_{1}:\left\{ \left( {x\quad \gamma^{r}} \right) \right\}},} & {\left( {x\quad \gamma^{r}} \right):} & \left. a\mapsto b_{1} \right. \\ {{{OP}_{2}:\left\{ {\left( {x\quad \gamma^{r}} \right),\left( {x\quad \gamma^{r}} \right)} \right\}},} & {{\left( {x\quad \gamma^{r}} \right) \circ \left( {x\quad \gamma^{r}} \right)}:} & \left. a\mapsto b_{2} \right. \\ {{{OP}_{3}:\left\{ {\left( {x\quad \gamma^{r}} \right),\left( {x\quad \gamma^{r}} \right),\left( {x\quad \gamma^{r}} \right)} \right\}},} & {{\left( {x\quad \gamma^{r}} \right) \circ \left( {x\quad \gamma^{r}} \right) \circ \left( {x\quad \gamma^{r}} \right)}:} & \left. a\mapsto b_{3} \right. \\ {\cdots \quad \cdots} & {\cdots \quad \cdots} & {\cdots \quad \cdots} \\ {{OP}_{k}:\left\{ {\left( {x\quad \gamma^{r}} \right),\left( {x\quad \gamma^{r}} \right),\left( {x\quad \gamma^{r}} \right),\ldots \quad,\left( {x\quad \gamma^{r}} \right)} \right\}} & {{\left( {x\quad \gamma^{r}} \right) \circ \left( {x\quad \gamma^{r}} \right) \circ \left( {x\quad \gamma^{r}} \right) \circ \quad \ldots \quad \circ \left( {x\quad \gamma^{r}} \right) \circ}:} & \left. a\mapsto b_{k} \right. \end{matrix}$

[0117] Then, when making the matrix comprised by di rows and “m” columns expressing the first linear transform D Mr, the above (2-11) is indicated by the following (2-12): $\begin{matrix} \begin{matrix} {\left\{ M_{r} \right\},} & {M_{r}:\left. a\mapsto b_{1} \right.} \\ {\left\{ {M_{r},M_{r}} \right\},} & {M_{r}^{2}:\left. a\mapsto b_{2} \right.} \\ {\left\{ {M_{r},M_{r},M_{r}} \right\},} & {M_{r}^{3}:\left. a\mapsto b_{3} \right.} \\ {\cdots \quad \cdots \quad \cdots \quad \cdots} & \cdots \\ {\left\{ {M_{r},M_{r},M_{r},\ldots \quad,M_{r}} \right\},} & {M_{r}^{k}:\left. a\mapsto b_{k} \right.} \end{matrix} & \left( {2\text{-}12} \right) \end{matrix}$

[0118] The matrix Mr of k·dixm obtained by vertically arranging matrixes Mr to Mr^(k) comprised by di rows and “m” columns expressing the combination of the transform strings defined by above OP₁ to OP_(K) is indicated by the following (2-13):

[0119] Here, Mr^(x) (x is an integer satisfying 1≦x≦k) is the matrix obtained by combining X number of Mrs. $\begin{matrix} {M:={{\begin{pmatrix} M_{r} \\ M_{r}^{2} \\ \cdots \\ M_{r}^{k} \end{pmatrix}:\left. a\mapsto\begin{pmatrix} b_{1} \\ b_{2} \\ \cdots \\ b_{k} \end{pmatrix} \right.} = \begin{pmatrix} {\gamma^{r} \cdot a} \\ {\gamma^{2r} \cdot a} \\ \cdots \\ {\gamma^{kr} \cdot a} \end{pmatrix}}} & \left( {2\text{-}13} \right) \end{matrix}$

[0120] As shown in above (2-13), the matrix M defines “k” number of processings each performing γ^(r) to γ^(kr)-times multiprocessings (*γ^(r)) on the data a.

[0121] In this case, as shown in FIG. 12, the CPU 34 generates design data indicating the design of a processing circuit 11 having the processing circuits 21 ₁ to 21 _(k) each performing γ^(r) to γ^(kr)-times multiprocessings (*γ^(r)) on the data FS0.

[0122] As explained above, in the circuit design method of the present embodiment, at step ST13 shown in FIG. 8, second processings performing the same processing on the same data among the pluralities of second processings forming each of the plurality of first processings (D-times multiprocessings and α-times multiprocessings) are identified.

[0123] Then, at step ST14, the processing circuits 11 and 11 a comprising a first processing circuit shared by the plurality of first processings and performing the identified second processings and a second processing circuit for performing the processings other than the identified second processings among the pluralities of second processings forming each of the plurality of first processings are designed.

[0124] For this reason, according to the circuit design method of the present embodiment, the processing circuits 11 and 11 a can be designed to be small in scale.

[0125] Further, in the circuit design method of the present embodiment, at step ST12 shown in FIG. 8, for each of the plurality of processings performed by the processing circuit 11 indicated in the above (2-7) input at step ST11, a matrix M indicated in the above (2-9) for performing the second linear transforms (first processings) obtained by combining the number of first linear transforms D corresponding to the predetermined number of times is generated. The processings of steps ST13 and ST14 mentioned above are carried out with respect to this.

[0126] For this reason, according to the circuit design method of the present embodiment, the processing circuits 11 and 11 a can be designed to be small in scale and, at the same time, the processing time can be shortened.

[0127] Further, in the circuit design method of the present embodiment, as shown in FIG. 9 and FIG. 11, the processing circuit 11 performs the first processings in parallel on the data FS0, so the processing time can be further shortened.

[0128] Namely, the processing circuits 21 ₁ to 21 _(k) process the data FS0 (data “a”) in parallel, so all of the data b₁ to b_(k) (data OUT₁ to OUT_(K)) can be obtained at approximately the same timing.

[0129] For this reason, a processing circuit 11 shortening the time from when the data FS0 is input to when the data b₂ to b_(k) are obtained over the design shown in FIG. 3 can be designed.

[0130] [Second Embodiment]

[0131] In the present embodiment, the case where 4 bits of data D (=D[3], D[2], D[1], D[0]) treated as dimensions on the finite field F(2⁴) are regarded as vertical vectors, and a circuit for applying two linear transforms indicated by the matrixes M1 and M2 shown in the following (2-14) and (2-15) with respect to the related data D is designed will be exemplified. $\begin{matrix} {{M1} = \begin{pmatrix} 1 & 1 & 0 & 1 \\ 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0 \end{pmatrix}} & \left( {2\text{-}14} \right) \\ {{M2} = \begin{pmatrix} 0 & 1 & 0 & 1 \\ 1 & 0 & 1 & 1 \\ 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 \end{pmatrix}} & \left( {2\text{-}15} \right) \end{matrix}$

[0132] Conventionally, the output values E1=M1·D and E2=M2·D are expressed as vertical vectors and indicated by the following (2-16) and (2-17): $\begin{matrix} \begin{matrix} {{E1} = \left( {{{E1}\lbrack 3\rbrack},{{E1}\lbrack 2\rbrack},{{E1}\lbrack 1\rbrack},{{E1}\lbrack 0\rbrack}} \right.} \\ {= \left( {{{D\lbrack 1\rbrack} + {D\lbrack 2\rbrack}},{D\lbrack 3\rbrack},{{D\lbrack 0\rbrack} + {D\lbrack 2\rbrack}},{{D\lbrack 0\rbrack} + {D\lbrack 1\rbrack} + {D\lbrack 3\rbrack}}} \right)} \end{matrix} & \left( {2\text{-}16} \right) \\ \begin{matrix} {{E2} = \left( {{{E2}\lbrack 3\rbrack},{{E2}\lbrack 2\rbrack},{{E2}\lbrack 1\rbrack},{{E2}\lbrack 0\rbrack}} \right.} \\ {= \left( {{D\lbrack 1\rbrack},{D\lbrack 0\rbrack},{{D\lbrack 0\rbrack} + {D\lbrack 2\rbrack} + {D\lbrack 3\rbrack}},{{D\lbrack 1\rbrack} + {D\lbrack 2)}}} \right.} \end{matrix} & \left( {2\text{-}17} \right) \end{matrix}$

[0133] In the conventional circuit design method, as shown in FIG. 13, a processing circuit 401 comprising a processing circuit 402 for performing the processing shown in the above (2-16) and a processing circuit 403 for performing the processing shown in the above (2-17) is designed.

[0134] The processing circuit 402 is comprised of adder circuits 411, 412, 413, and 414.

[0135] Further, the processing circuit 403 is comprised of adder circuits 421, 422, and 423.

[0136] The circuit design method of the present embodiment is the same in that it applies the linear transforms expressed by the matrixes M1 and M2 shown in the above (2-14) and (2-15) to 4 bits of data D (=D[3], D[2], D[1], D[0]) handled as dimensions on the finite field F(2⁴).

[0137] In the present embodiment, in place of using two 4×4 matrixes, use is made of the matrix M shown in the following (2-18) connecting the matrixes M1 and M2: $\begin{matrix} {M = {\begin{pmatrix} {M1} \\ {M2} \end{pmatrix} = \begin{pmatrix} 1 & 1 & 0 & 1 \\ 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0 \\ 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 \\ 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 \end{pmatrix}}} & \left( {2\text{-}18} \right) \end{matrix}$

[0138] In the circuit design method of the present embodiment, the processing of the above matrix M is carried out and, in the processings among the above (2-16) and (2-17), “D[0]+D[2]” and “D[1]+D[2]”, which are common second processings, are identified among the plurality of second processings forming the first processing corresponding to the matrix M1 and the first processing corresponding to the matrix M2.

[0139] Then, as shown in FIG. 14, the adder circuits 412 and 421 shown in FIG. 13 for performing the second processing “D[0]+D[2]” and the adder circuits 413 and 422 shown in FIG. 13 for performing the second processing “D[1]+D[2]” are shared, so the adder circuits 412 and 413 are deleted. Therefore, a processing circuit 401 having a circuit scale reduced in comparison with the processing circuit 401 shown in FIG. 13 is designed.

[0140] By this, a processing circuit 403 shown in FIG. 14 for performing the same processing as the processing circuit 401 shown in FIG. 13 can be designed in a smaller scale in comparison with the processing circuit 401.

[0141] The present invention is not limited to the above embodiments.

[0142] As another embodiment, it is also possible to use a base shown in the following (2-19) as the above predetermined base, show the above data “a” as in the following (2-20), and show the data “a” as in the following (2-21) as the m-th dimension vector: $\begin{matrix} \left\{ {1,\gamma,\gamma^{2},\ldots \quad,\gamma^{m - 1}} \right\} & \left( {2\text{-}19} \right) \\ {a = {a_{0} + {a_{1}\gamma} + {a_{2}\gamma^{2}} + {a_{3}\gamma^{3}} + \ldots \quad + {a_{m - 1}\gamma^{m - 1}}}} & \left( {2\text{-}20} \right) \\ {a = \begin{pmatrix} a_{0} \\ a_{1} \\ a_{2} \\ \vdots \\ a_{m - 1} \end{pmatrix}} & \left( {2\text{-}21} \right) \end{matrix}$

[0143] Summarizing the effects of the invention, as explained above, according to the present invention, it is possible to provide a circuit design method, apparatus, and program able to design a processing circuit to be small in scale when designing a processing circuit for performing a plurality of different processings on predetermined data.

[0144] While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention. 

1. A circuit design method executed by a computer for designing a processing circuit for applying a plurality of different first processings to predetermined data comprising: a first step of identifying second processings performing the same processing on the same data in pluralities of second processings forming each of said plurality of first processings and a second step of designing a processing circuit comprising a first processing circuit shared by said plurality of first processings and performing said second processings identified in said first step and a second processing circuit for performing processings other than said second processings identified in said first step in said pluralities of second processings forming each of said plurality of first processings.
 2. A circuit design method as set forth in claim 1, wherein: said first processings are linear transform processings, and said second processings are addition.
 3. A circuit design method as set forth in claim 1, further comprising, when said plurality of first processings are processings applying first linear transforms to said predetermined data different predetermined number of times, a third step of defining a second linear transform combining a number of first linear transforms corresponding to the predetermined number of times of processing for each of the plurality of first processings, and in said first step, identifying said second processings performing the same processing on the same data among said plurality of second processings forming said second linear transform defined for each of said plurality of first processings at said third step.
 4. A circuit design method as set forth in claim 3, further comprising, in said second step, designing said processing circuit so as to perform said plurality of first processings in parallel on said predetermined data based on said second linear transforms defined in said third step.
 5. A circuit design method as set forth in claim 3, wherein: said predetermined data is expressed by a vector by a predetermined base on a predetermined linear space, and said linear transforms are transforms defined on said linear space.
 6. A circuit design method as set forth in claim 3, further comprising, when said predetermined linear space is indicated by the following (3-1), said data “a” of the predetermined data is indicated as the m-th dimension vector by the following (3-4) when using the base shown in the following (3-2) as the predetermined base and said data “a” is indicated as in the following (3-3), said first linear transform is defined as the linear transform D on the linear space shown in the following (3-1), the data “b” of the result of the above plurality of processings is shown as the k-th dimension vector by the following (3-5), and the data bi indicating the results of the processings forming the data “b” shown in the following (3-5) is shown as the di-th dimension vector by the following (3-6), defining the matrix M comprised by di rows and “m” columns, performing said second linear transforms, and shown by the following (3-7) in said third step and identifying said second processings performing the same processing on the same data among said plurality of second processings based on the following (3-7) defined in said third step in said first step, where, “m” and di are integers of 2 or more, the predetermined number of times corresponding to at least one of the above plurality of processings is 2 or more, and “k” is an integer of 2 or more: $\begin{matrix} {{Linear}\quad {space}\quad {Fg}^{m}} & \left( {3\text{-}1} \right) \\ \left\{ {\gamma_{1},\gamma_{2},\ldots \quad,\gamma_{m}} \right\} & \left( {3\text{-}2} \right) \\ {a = {{a_{1}\gamma_{1}} + {a_{2}\gamma_{2}} + {\ldots \quad a_{m}\gamma_{m}}}} & \left( {3\text{-}3} \right) \\ {a = \begin{pmatrix} a_{1} \\ a_{2} \\ \vdots \\ a_{m} \end{pmatrix}} & \left( {3\text{-}4} \right) \\ {b = \begin{pmatrix} b_{1} \\ b_{2} \\ \vdots \\ b_{k} \end{pmatrix}} & \left( {3\text{-}5} \right) \\ {b_{i} = \begin{pmatrix} b_{i,1} \\ b_{i,2} \\ \vdots \\ b_{i,{di}} \end{pmatrix}} & \left( {3\text{-}6} \right) \\ {M = \begin{pmatrix} D \\ D^{2} \\ \vdots \\ D^{K} \end{pmatrix}} & \left( {3\text{-}7} \right) \end{matrix}$


7. A circuit design method as set forth in claim 6, wherein when using the base shown by the following (3-8) as said predetermined base and said data “a” is shown as in the following (3-9), said data “a” is shown by the following (3-10) as an m-th dimension vector: $\begin{matrix} \left\{ {1,\gamma,\gamma^{2},\ldots \quad,\gamma^{m - 1}} \right\} & \left( {3\text{-}8} \right) \\ {a = {a_{0} + {a_{1}\gamma} + {a_{2}\gamma^{2}} + {a_{3}\gamma^{3}} + \ldots \quad + {a_{m - 1}\gamma^{m - 1}}}} & \left( {3\text{-}9} \right) \\ {a = \begin{pmatrix} a_{0} \\ a_{1} \\ a_{2} \\ \vdots \\ a_{m - 1} \end{pmatrix}} & \left( {3\text{-}10} \right) \end{matrix}$


8. A circuit design method as set forth in claim 6, wherein said third step defines said matrix M comprised of said matrixes D for performing γ^(r)-times multiprocessing based on the dimension γ on said linear space.
 9. A circuit design apparatus of a processing circuit for applying a plurality of different first processings to predetermined data comprising: a first means for identifying second processings performing the same processing on the same data in pluralities of second processings forming each of said plurality of first processings and a second means for designing a processing circuit comprising a first processing circuit shared by said plurality of first processings and performing said second processings identified by said first means and a second processing circuit for performing processings other than said second processings identified by said first means in said pluralities of second processings forming each of said plurality of first processings.
 10. A program executed in a circuit design apparatus of a processing circuit for applying a plurality of different first processings to predetermined data comprising: a first routine of identifying second processings performing the same processing on the same data in pluralities of second processings forming each of said plurality of first processings and a second routine of designing a processing circuit comprising a first processing circuit shared by said plurality of first processings and performing said second processings identified in said first routine and a second processing circuit for performing processings other than said second processings identified in said first routine in said pluralities of second processings forming each of said plurality of first processings. 